EPM9560RC-15 vs EPM9560RC-10 Comparison
Detailed side-by-side comparison of EPM9560RC-15 by Altera and EPM9560RC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC-15
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 β Last Time BuyIntel
EPM9560RC-10
EPM9560RC-10 - MAX 9000 CPLD, 560 Macrocells, 240-pin PGA | Intel
EPM9560RC-10 ObsoleteSpecification Comparison
| Parameter | EPM9560RC-15 | EPM9560RC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $30.10 | $110.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| Maximum User I/O Pins | 191 | 212 |
| Pin-to-Pin Delay (tPD1) | 15 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Package | 240-pin RQFP (32x32 mm) | 240-pin PGA (RC suffix) |
| Mounting Type | Surface Mount | Through-Hole / Socketed |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array Matrix (MAX) - third generation |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | IEEE 1149.1 JTAG |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |