EPM9560RC208-12 vs EPM9560RC208-10 Comparison
Detailed side-by-side comparison of EPM9560RC208-12 by Altera and EPM9560RC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-12 | EPM9560RC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $15.40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | β |
| Usable Gates | 12000 | 12,000 |
| User I/O Lines | 153 | β |
| Propagation Delay (tPD) | 12 ns | β |
| Maximum Clock Frequency | 125 MHz | β |
| Supply Voltage (VCCINT) | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| Package | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (in-system programmable via JTAG) |
| Logic Array Blocks | 20 | β |
| Speed Grade | -12 (12 ns) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in retrieved distributor listings] |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/O Pins | β | 212 (208-pin package variant) |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Frequency (fMAX) | β | [DATA_NEEDED: internal toggle frequency in MHz] |
| I/O Standards Supported | β | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) |
| Process Technology | β | 0.30 Β΅m CMOS EEPROM |
| Lead-Free | β | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] |
| Programmability | β | JTAG (IEEE 1149.1) in-system programming |