EPM9560RC208-12 vs EPM9560RC208-17 Comparison
Detailed side-by-side comparison of EPM9560RC208-12 by Altera and EPM9560RC208-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-12 | EPM9560RC208-17 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $54.75 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | β |
| Macrocells | 560 | β |
| Flip-Flops | 772 | β |
| Usable Gates | 12000 | 12,000 |
| User I/O Lines | 153 | β |
| Propagation Delay (tPD) | 12 ns | β |
| Maximum Clock Frequency | 125 MHz | β |
| Supply Voltage (VCCINT) | 5 V | β |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| Package | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (RC208) |
| Terminal Pitch | 0.50 mm | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | β |
| Logic Array Blocks | 20 | β |
| Speed Grade | -12 (12 ns) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Product Type | β | CPLD (EPLD, in-system programmable) |
| Macro Cells | β | 560 |
| Logic Array Blocks (LABs) | β | 16 |
| Pin-to-Pin Delay (tPD) | β | 17 ns |
| Maximum Counter Frequency | β | 117.6 MHz |
| User I/O Pins | β | 212 |
| Supply Voltage (VCC) | β | 5 V |
| Programming Technology | β | EEPROM (in-system programmable) |
| Program/Erase Cycles | β | 100 minimum |
| JTAG (IEEE 1149.1) Support | β | Yes |
| Architecture | β | Third-generation MAX (AND-OR PLA) |