EPM9560RC208-14 vs EPM9560RC208-18 Comparison

Detailed side-by-side comparison of EPM9560RC208-14 by Altera and EPM9560RC208-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC208-18 EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 βœ— End of Life

Specification Comparison

Parameter EPM9560RC208-14 EPM9560RC208-18
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Eol
Stock Status In Stock In Stock
Unit Price (USD) $27.90 $0.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Usable Gates 12,000 12,000 gates
Macrocells 560 560 macrocells
Logic Array Blocks (LABs) 16 β€”
User I/O Pins 149 β€”
Maximum Operating Frequency 117.6 MHz 117.6 MHz (family -15 grade reference)
Pin-to-Pin Propagation Delay 14 ns β€”
Supply Voltage 5 V 5 V
I/O Voltage Support 3.3 V / 5 V β€”
Program Memory Type EEPROM (non-volatile) β€”
In-System Programmability Yes (JTAG, IEEE 1149.1) β€”
Package 208-pin RQFP (PQFP) 208-pin RQFP (Power Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Process Technology 0.35 Β΅m CMOS EEPROM β€”
RoHS Status Non-compliant (legacy part) [DATA_NEEDED: RoHS status]
Device Family β€” MAX 9000 (EPM9560)
Logic Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Propagation Delay (tPD) β€” 18 ns (speed grade -18)
I/O Voltage Compatibility β€” 3.3 V or 5 V
User I/O Lines β€” 149 I/O lines
Flip-Flops β€” 772 flip-flops
Package JESD-30 Code β€” S-PQFP-G208
Configuration Memory β€” EEPROM (non-volatile, no external config PROM)
Technology β€” CMOS
Operating Temperature β€” [DATA_NEEDED: operating temperature range]
Lifecycle Status β€” EOL / mature (per Altera product discontinuance notice)

Datasheets & Resources

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