EPM9560RC208-15 vs EPM9560ARC208-10 Comparison
Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteIntel
EPM9560ARC208-10
EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel
EPM9560ARC208-10 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-15 | EPM9560ARC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macro Cells | 560 macro cells | β |
| Pin-to-Pin Delay | 15 ns | β |
| Counter Speed | 117.6 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | β |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | 35 LABs |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns pin-to-pin) | β |
| Architecture | Third-generation Multiple Array MatriX (MAX) | β |
| Device Family | β | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 560 macrocells |
| User I/O Pins | β | 153 I/O |
| Propagation Delay (tPD) | β | 10 ns (speed grade -10) |
| Internal Frequency | β | 144.9 MHz |
| Logic Family | β | CMOS |
| JTAG Interface | β | IEEE 1149.1 boundary-scan (ISP) |
| Pin Count | β | 208 pins |