EPM9560RC208-15 vs EPM9560RC208-14 Comparison

Detailed side-by-side comparison of EPM9560RC208-15 by Altera and EPM9560RC208-14 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC208-15

EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-15 Obsolete
Altera
EPM9560RC208-14

EPM9560RC208-14 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera

EPM9560RC208-14 Obsolete

Specification Comparison

Parameter EPM9560RC208-15 EPM9560RC208-14
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $27.90
Family MAX 9000 MAX 9000
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 gates 12,000
Macro Cells 560 macro cells β€”
Pin-to-Pin Delay 15 ns β€”
Counter Speed 117.6 MHz β€”
Supply Voltage 5.0 V 5 V
Configuration Technology EEPROM (non-volatile) β€”
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (JTAG, IEEE 1149.1)
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PQFP)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
Number of I/O Pins [DATA_NEEDED: number of I/O pins] β€”
Logic Array Blocks [DATA_NEEDED: number of logic array blocks] β€”
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (legacy part)
Speed Grade -15 (15 ns pin-to-pin) β€”
Architecture Third-generation Multiple Array MatriX (MAX) β€”
Macrocells β€” 560
Logic Array Blocks (LABs) β€” 16
User I/O Pins β€” 149
Maximum Operating Frequency β€” 117.6 MHz
Pin-to-Pin Propagation Delay β€” 14 ns
I/O Voltage Support β€” 3.3 V / 5 V
Program Memory Type β€” EEPROM (non-volatile)
Process Technology β€” 0.35 Β΅m CMOS EEPROM

Datasheets & Resources

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