EPM9560RC208-17 vs EPM9560RC208-12 Comparison
Detailed side-by-side comparison of EPM9560RC208-17 by Altera and EPM9560RC208-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-17 | EPM9560RC208-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $54.75 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (EPLD, in-system programmable) | β |
| Usable Gates | 12,000 | 12000 |
| Macro Cells | 560 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Pin-to-Pin Delay (tPD) | 17 ns | β |
| Maximum Counter Frequency | 117.6 MHz | β |
| User I/O Pins | 212 | β |
| Supply Voltage (VCC) | 5 V | β |
| Package | 208-pin RQFP (RC208) | 208-pin RQFP (S-PQFP-G208) |
| Programming Technology | EEPROM (in-system programmable) | β |
| Program/Erase Cycles | 100 minimum | β |
| JTAG (IEEE 1149.1) Support | Yes | β |
| Architecture | Third-generation MAX (AND-OR PLA) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Device Type | β | EEPROM-based CPLD |
| Macrocells | β | 560 |
| Flip-Flops | β | 772 |
| User I/O Lines | β | 153 |
| Propagation Delay (tPD) | β | 12 ns |
| Maximum Clock Frequency | β | 125 MHz |
| Supply Voltage (VCCINT) | β | 5 V |
| I/O Voltage Compatibility | β | 3.3 V or 5 V |
| Terminal Pitch | β | 0.50 mm |
| Operating Temperature | β | 0C to +70C (commercial) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Logic Array Blocks | β | 20 |
| Speed Grade | β | -12 (12 ns) |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |