EPM9560RC208-17 vs EPM9560RC208-15 Comparison

Detailed side-by-side comparison of EPM9560RC208-17 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC208-17

EPM9560RC208-17 - MAX 9000 CPLD 12K Gates 560 Macro Cells | Altera

EPM9560RC208-17 Nrnd
Altera
EPM9560RC208-15

EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-15 Obsolete

Specification Comparison

Parameter EPM9560RC208-17 EPM9560RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $54.75 $0.00
Family MAX 9000 MAX 9000
Product Type CPLD (EPLD, in-system programmable) β€”
Usable Gates 12,000 12,000 gates
Macro Cells 560 560 macro cells
Logic Array Blocks (LABs) 16 β€”
Pin-to-Pin Delay (tPD) 17 ns β€”
Maximum Counter Frequency 117.6 MHz β€”
User I/O Pins 212 β€”
Supply Voltage (VCC) 5 V β€”
Package 208-pin RQFP (RC208) 208-pin RQFP (Power Quad Flat Pack)
Programming Technology EEPROM (in-system programmable) β€”
Program/Erase Cycles 100 minimum β€”
JTAG (IEEE 1149.1) Support Yes β€”
Architecture Third-generation MAX (AND-OR PLA) Third-generation Multiple Array MatriX (MAX)
Mounting Type Surface Mount Surface Mount
Device Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Pin-to-Pin Delay β€” 15 ns
Counter Speed β€” 117.6 MHz
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Operating Temperature β€” [DATA_NEEDED: operating temperature range]
Number of I/O Pins β€” [DATA_NEEDED: number of I/O pins]
Logic Array Blocks β€” [DATA_NEEDED: number of logic array blocks]
RoHS Status β€” [DATA_NEEDED: RoHS status]
Speed Grade β€” -15 (15 ns pin-to-pin)

Datasheets & Resources

Browse All Products Create BOM Request Quote