EPM9560RC208-17 vs EPM9560RC208-19 Comparison
Detailed side-by-side comparison of EPM9560RC208-17 by Altera and EPM9560RC208-19 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-17
EPM9560RC208-17 - MAX 9000 CPLD 12K Gates 560 Macro Cells | Altera
EPM9560RC208-17 NrndAltera
EPM9560RC208-19
EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera
EPM9560RC208-19 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-17 | EPM9560RC208-19 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $54.75 | $16.20 |
| Family | MAX 9000 | β |
| Product Type | CPLD (EPLD, in-system programmable) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | β |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | 17 ns | β |
| Maximum Counter Frequency | 117.6 MHz | β |
| User I/O Pins | 212 | 149 |
| Supply Voltage (VCC) | 5 V | β |
| Package | 208-pin RQFP (RC208) | RQFP-208 (208-pin PQFP) |
| Programming Technology | EEPROM (in-system programmable) | β |
| Program/Erase Cycles | 100 minimum | β |
| JTAG (IEEE 1149.1) Support | Yes | β |
| Architecture | Third-generation MAX (AND-OR PLA) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Device Family | β | MAX 9000 |
| Macrocells | β | 560 |
| Flip-Flops | β | 772 |
| Propagation Delay (tPD) | β | 19 ns |
| Maximum Frequency | β | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCCINT) | β | 5.0 V |
| I/O Voltage Tolerance | β | 3.3 V / 5 V |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Technology | β | CMOS EEPROM |
| JEDEC Package Code | β | S-PQFP-G208 |
| Operating Temperature | β | [DATA_NEEDED: operating temperature grade] |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |