EPM9560RC208-17 vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560RC208-17 by Altera and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-17 | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $54.75 | $0.00 |
| Family | MAX 9000 | β |
| Product Type | CPLD (EPLD, in-system programmable) | β |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Pin-to-Pin Delay (tPD) | 17 ns | 20 ns |
| Maximum Counter Frequency | 117.6 MHz | β |
| User I/O Pins | 212 | 153 |
| Supply Voltage (VCC) | 5 V | β |
| Package | 208-pin RQFP (RC208) | 208-pin RQFP (28x28 mm) |
| Programming Technology | EEPROM (in-system programmable) | β |
| Program/Erase Cycles | 100 minimum | β |
| JTAG (IEEE 1149.1) Support | Yes | β |
| Architecture | Third-generation MAX (AND-OR PLA) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Device Family | β | MAX 9000 (EPM9560) |
| Macrocells | β | 560 |
| Logic Array Blocks | β | 35 |
| Maximum Clock Frequency | β | 100 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature | β | 0C to +70C (commercial) |
| I/O Standards | β | 5.0 V TTL/CMOS compatible |
| Flip-Flops | β | 772 |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |
| MSL Level | β | [DATA_NEEDED: MSL level] |