EPM9560RC208-18 vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-18
EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-18 β End of LifeIntel
EPM9560RC208-20
EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel
EPM9560RC208-20 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Eol | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Usable Gates | 12,000 gates | 12,000 |
| Macrocells | 560 macrocells | 560 |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | β |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | β |
| Supply Voltage | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| User I/O Lines | 149 I/O lines | β |
| Flip-Flops | 772 flip-flops | 772 |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (28x28 mm) |
| Package JESD-30 Code | S-PQFP-G208 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | β |
| Technology | CMOS | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | β |
| Logic Array Blocks | β | 35 |
| User I/O Pins | β | 153 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Clock Frequency | β | 100 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| I/O Standards | β | 5.0 V TTL/CMOS compatible |
| MSL Level | β | [DATA_NEEDED: MSL level] |