EPM9560RC208-19 vs EPM9560RC208-15 Comparison

Detailed side-by-side comparison of EPM9560RC208-19 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-19 EPM9560RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.20 $0.00
Device Family MAX 9000 β€”
Product Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 560 β€”
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] β€”
Flip-Flops 772 β€”
User I/O Pins 149 β€”
Propagation Delay (tPD) 19 ns β€”
Maximum Frequency [DATA_NEEDED: fMAX] β€”
Supply Voltage (VCCINT) 5.0 V β€”
I/O Voltage Tolerance 3.3 V / 5 V β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes, via IEEE Std. 1149.1 JTAG
Technology CMOS EEPROM β€”
Package RQFP-208 (208-pin PQFP) 208-pin RQFP (Power Quad Flat Pack)
JEDEC Package Code S-PQFP-G208 β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Family β€” MAX 9000
Device Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells β€” 560 macro cells
Pin-to-Pin Delay β€” 15 ns
Counter Speed β€” 117.6 MHz
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile)
Number of I/O Pins β€” [DATA_NEEDED: number of I/O pins]
Logic Array Blocks β€” [DATA_NEEDED: number of logic array blocks]
Speed Grade β€” -15 (15 ns pin-to-pin)
Architecture β€” Third-generation Multiple Array MatriX (MAX)

Datasheets & Resources

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