EPM9560RC208-20C vs EPM9560RC210-20 Comparison

Detailed side-by-side comparison of EPM9560RC208-20C by Altera and EPM9560RC210-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC208-20C

EPM9560RC208-20C - MAX 9000 CPLD 560 Macro Cells | Altera

EPM9560RC208-20C Obsolete
Altera
EPM9560RC210-20

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-20C EPM9560RC210-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $60.00
Family MAX 9000 MAX 9000
Device Type EEPROM-based CPLD (EE PLD) β€”
Macrocells 560 560
Usable Gates 12,000 12,000
Flip-Flops 772 β€”
Configurable I/O Lines 149 β€”
Propagation Delay (tPD) 20 ns (speed grade -20) β€”
Maximum Frequency 100 MHz β€”
Supply Voltage 5.0 V 5 V
I/O Voltage Support 3.3 V or 5 V β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (MAX+PLUS II flow)
Package 208-pin RQFP (Power Quad Flat Pack) RQFP-210 (Power Quad Flat Pack, 0.5mm pitch)
JESD-30 Package Code S-PQFP-G208 β€”
Terminal Form Gull Wing β€”
Operating Temperature Grade Commercial (0C to +70C) β€”
Technology CMOS β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] RoHS3 Compliant (per supplier listing)
Product Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 16
Pin-to-Pin Delay (tPD) β€” 20 ns
Clock-to-Output (tCO) β€” 12 ns
Maximum User I/O β€” [DATA_NEEDED: 212 I/O per datasheet, package-dependent]
Process Technology β€” 0.65 um EEPROM
Boundary-Scan (JTAG) β€” IEEE Std 1149.1 compliant
Operating Temperature β€” [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist]

Datasheets & Resources

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