EPM9560RC208-20N vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560RC208-20N by Intel and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-20N | EPM9560RC208-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay (tPD) | 20 ns | β |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (28x28 mm) |
| User I/O Pins | 149 | 153 |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS Status | Lead-free (N suffix) | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | β |
| Flip-Flops | 772 (per EPM9560 series data) | 772 |
| Speed Grade | -20 (20 ns) | β |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Logic Array Blocks | β | 35 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Clock Frequency | β | 100 MHz |
| I/O Standards | β | 5.0 V TTL/CMOS compatible |