EPM9560RC208-20N vs EPM9560WC208-20C Comparison
Detailed side-by-side comparison of EPM9560RC208-20N by Intel and EPM9560WC208-20C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-20N | EPM9560WC208-20C |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $140.00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EE PLD) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | β |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| User I/O Pins | 149 | 149 |
| Supply Voltage | 5.0 V | 3.3 V or 5 V (configurable I/O) |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| JTAG Interface | IEEE Std. 1149.1 | β |
| Mounting Type | Surface Mount | Surface Mount (Ceramic QFP) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | Lead-free (N suffix) | ROHS3 Compliant (per fpgalink listing) |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | β |
| Flip-Flops | 772 (per EPM9560 series data) | β |
| Speed Grade | -20 (20 ns) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Series | β | EPM9560 |
| Logic Array Blocks (LABs) | β | 35 |
| Maximum Clock Frequency | β | [DATA_NEEDED: fMAX value not in verified data] |
| Process Technology | β | CMOS, Electrically Erasable |
| Pin Count | β | 208 |
| Programming Interface | β | JTAG BST (in-system programmable) |
| Operating Temperature Grade | β | Commercial (C suffix) |
| Moisture Sensitivity Level | β | MSL 3 (168 Hours) |