EPM9560RC208-3 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-3 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera
EPM9560RC208-3 β Last Time BuySpecification Comparison
| Parameter | EPM9560RC208-3 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $58.50 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Usable Gates | 12,000 | 12,000 gates |
| Maximum Operating Frequency | [DATA_NEEDED: f_MAX] | β |
| Pin-to-Pin Delay (speed grade -3) | approximately 3 ns (slowest grade) | β |
| Speed Grade | -3 | -15 (15 ns pin-to-pin) |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| I/O Voltage Tolerance | 5V | β |
| Process Technology | 0.5 Β΅m CMOS EPROM | β |
| Programming Interface | ByteBlaster / BitBlaster (JTAG-compatible) | β |
| Operating Temperature | [DATA_NEEDED: industrial / commercial range] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Lifecycle | Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) | β |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Mounting Type | β | Surface Mount |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |