EPM9560RC208-4C vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-4C by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-4C
EPM9560RC208-4C - MAX 9000 CPLD 560 Macrocell | Altera
EPM9560RC208-4C ObsoleteAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-4C | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 (EPM9560) | β |
| Macrocells | 560 | β |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 12 | β |
| Maximum User I/O Pins | 164 | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -4 (12 ns pin-to-pin) | -15 (15 ns pin-to-pin) |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature Range | 0C to +70C (commercial) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Pin-to-Pin Delay | 12 ns | 15 ns |
| Maximum System Frequency | 125 MHz | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Manufacturer | Altera Corporation | β |
| Family | β | MAX 9000 |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 macro cells |
| Counter Speed | β | 117.6 MHz |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |