EPM9560RC208-9 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-9 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-9
EPM9560RC208-9 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Altera
EPM9560RC208-9 NrndAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-9 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $71.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD / EPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | β |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | β |
| User I/O Pins | 212 | β |
| Pin-to-Pin Delay (tPD) | 9 ns | β |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX from datasheet] | β |
| Core Voltage | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Programmability | In-system programmable (JTAG) | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -9 | -15 (15 ns pin-to-pin) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | EPROM-based (one-time programmable) / UV-erasable | β |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |