EPM9560RC210-20 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC210-20 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC210-20
EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
EPM9560RC210-20 β Last Time BuyAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9560RC210-20 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $60.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 560 | β |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | β |
| Package | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Clock-to-Output (tCO) | 12 ns | β |
| Maximum User I/O | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] | β |
| Supply Voltage | 5 V | 5.0 V |
| Process Technology | 0.65 um EEPROM | β |
| In-System Programmability | Yes (MAX+PLUS II flow) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | β |
| Operating Temperature | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | RoHS3 Compliant (per supplier listing) | [DATA_NEEDED: RoHS status] |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |