EPM9560RC240-15C vs EPM9560RC240-2 Comparison
Detailed side-by-side comparison of EPM9560RC240-15C by Intel and EPM9560RC240-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-15C | EPM9560RC240-2 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $180.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | β |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | β |
| Logic Array Blocks | 20 | β |
| User I/O Pins | 187 | β |
| Maximum Internal Frequency | 117.6 MHz | β |
| Propagation Delay (tPD) | 15 ns | β |
| Supply Voltage | 5.0 V | 5 V |
| Operating Voltage Range | 3.3 V or 5 V | β |
| Package | 240-pin RQFP (PowerQuad II) | 240-pin RQFP (Metric QFP) |
| Terminal Pitch | 0.5 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: commercial/industrial grade] |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes (ISP via JTAG) | β |
| JTAG Interface | IEEE 1149.1 boundary-scan | β |
| Process Technology | CMOS | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (5V RQFP, pre-RoHS era) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Logic Elements | β | 560 macrocells |
| Pin-to-Pin Delay | β | 2 ns (speed grade -2) |
| Maximum Frequency | β | 100 MHz |
| User I/O Count | β | 212 |
| Programming Interface | β | JTAG (IEEE 1149.1), in-system programmable |
| Non-Volatile Configuration | β | Yes (EEPROM-based) |
| Lead-Free | β | No (legacy Sn/Pb process) |
| Logic Block Count | β | [DATA_NEEDED: LAB count] |