EPM9560RC240-15N vs EPM9560RC240-12 Comparison
Detailed side-by-side comparison of EPM9560RC240-15N by Altera and EPM9560RC240-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC240-15N
EPM9560RC240-15N - MAX 9000 CPLD, 560 Macrocells, 15ns, RQFP-240
EPM9560RC240-15N NrndAltera
EPM9560RC240-12
EPM9560RC240-12 - 560 Macrocell EE PLD, 12ns PQFP-240 | Altera
EPM9560RC240-12 ObsoleteSpecification Comparison
| Parameter | EPM9560RC240-15N | EPM9560RC240-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.85 | $9.95 |
| Series | MAX 9000 | β |
| Family | MAX 9000 (third-generation Multiple Array MatriX) | MAX 9000 (EPM9560) |
| Usable Gates | 12,000 | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 20 |
| Maximum User I/O Pins | 216 | β |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | β |
| Internal Counter Frequency (fCNT) | 145 MHz | β |
| Global Setup Time (tFSU) | [DATA_NEEDED: tFSU for -15 grade] | β |
| Clock-to-Output Time (tFCO) | [DATA_NEEDED: tFCO for -15 grade] | β |
| Supply Voltage | 5.0 V | β |
| Logic Family | CMOS (EEPROM-based) | β |
| Programmability | In-system programmable (IEEE 1532/JTAG) | β |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | β |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature grade] |
| Package | RQFP-240 (240-pin Plastic Quad Flat Pack) | PQFP-240 (RC240) 0.500 mm pitch, gull-wing |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] | [DATA_NEEDED: RoHS compliance] |
| Device Type | β | EE PLD / CPLD |
| Flip-Flops | β | 772 |
| User I/O Pins | β | 191 |
| Maximum Propagation Delay (tPD) | β | 13.4 ns |
| Speed Grade | β | -12 (13.4 ns tPD) |
| Maximum Operating Frequency (estimated) | β | ~76 MHz registered |
| Core Supply Voltage (VCCINT) | β | 5 V |
| I/O Logic Levels | β | 3.3 V or 5 V (configurable) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Programming Interface | β | IEEE 1149.1 JTAG |
| Process Technology | β | CMOS |