EPM9560RC304-15 vs EPM9560RC304-15F Comparison

Detailed side-by-side comparison of EPM9560RC304-15 by Altera and EPM9560RC304-15F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC304-15 EPM9560RC304-15F
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.40 $18.75
Device Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX), EEPROM-based Multiple Array MatriX (MAX) with PIA interconnect
Macrocells 560 560
Logic Array Blocks (LABs) 16 16 (40 macrocells each)
User I/O Pins 212 (maximum) 212
Propagation Delay (tPD) 15 ns (combinatorial, pin-to-pin) β€”
Pin Count 304 β€”
Package 304-pin RQFP (Plastic Quad Flat Pack) RQFP-304 (304-pin Plastic QFP)
Supply Voltage (VCCINT) 5.0 V β€”
I/O Standard 5.0 V TTL / PCI-compliant β€”
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG β€”
Configuration Memory On-chip EEPROM (non-volatile) β€”
Technology Node High-performance CMOS, EEPROM process β€”
Operating Temperature [DATA_NEEDED: industrial/commercial temperature grade] -40C to +85C (industrial)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: lead-free / RoHS compliance status] [DATA_NEEDED: rohs status - not stated in source]
Series β€” EPM9560
Usable Gates β€” 12,000
Propagation Delay (tpd) β€” 16.6 ns (max)
Maximum Internal Frequency β€” 117.6 MHz
Core Supply Voltage β€” 5.0 V
Dedicated Inputs β€” 4
Programming Technology β€” 5.0 V in-system EEPROM via JTAG (IEEE 1149.1)
Boundary Scan Test (BST) β€” Yes, JTAG-compliant
Process Technology β€” High-performance CMOS, EEPROM-based
MSL Level β€” 3 (168 hours)

Datasheets & Resources

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