EPM9560RC304-15 vs EPM9560RC304C-3 Comparison

Detailed side-by-side comparison of EPM9560RC304-15 by Altera and EPM9560RC304C-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC304-15 EPM9560RC304C-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.40 $95.00
Device Family MAX 9000 β€”
Architecture Multiple Array MatriX (MAX), EEPROM-based β€”
Macrocells 560 β€”
Logic Array Blocks (LABs) 16 β€”
User I/O Pins 212 (maximum) 212
Propagation Delay (tPD) 15 ns (combinatorial, pin-to-pin) β€”
Pin Count 304 304
Package 304-pin RQFP (Plastic Quad Flat Pack) RBGGA-304 (Ceramic Ball Grid Array)
Supply Voltage (VCCINT) 5.0 V β€”
I/O Standard 5.0 V TTL / PCI-compliant β€”
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG β€”
Configuration Memory On-chip EEPROM (non-volatile) β€”
Technology Node High-performance CMOS, EEPROM process β€”
Operating Temperature [DATA_NEEDED: industrial/commercial temperature grade] 0 C to +70 C (Commercial)
Mounting Type Surface Mount Surface Mount (BGA)
RoHS Status [DATA_NEEDED: lead-free / RoHS compliance status] unknown (legacy part, pre-RoHS era)
Family β€” MAX 9000
Device Type β€” CPLD (EPLD)
Macrocells (Logic Elements) β€” 560
Usable Gates β€” 12,000
Speed Grade β€” -3 (3 ns pin-to-pin, commercial)
Supply Voltage β€” 5 V
Programmability β€” In-system, non-volatile EEPROM
JTAG Support β€” IEEE 1149.1 boundary-scan
Logic Blocks β€” Logic Array Blocks (LABs) with PIA interconnect

Datasheets & Resources

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