EPM9560RC304-20 vs EPM9560RC340-15 Comparison

Detailed side-by-side comparison of EPM9560RC304-20 by Altera and EPM9560RC340-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC304-20 EPM9560RC340-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $24.00
Device Family MAX 9000 (EPM9560) β€”
Macrocells 560 560
Usable Gates 12,000 12,000
User I/O Lines 212 β€”
Propagation Delay (tPD) 20 ns β€”
Maximum Operating Frequency 100 MHz β€”
Core Supply Voltage 5.0 V β€”
I/O Voltage 3.3 V or 5 V (configurable) β€”
Configuration Technology EEPROM (in-system programmable) β€”
JTAG Interface IEEE Std. 1149.1 (built-in) β€”
Package 304-pin RQFP 340-RQFP (Reduced Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
Logic Array Blocks (LABs) 20 β€”
Speed Grade -20 β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - not explicitly stated in verified data]
MSL Level [DATA_NEEDED: MSL level] β€”
Family β€” MAX 9000
Device Type β€” CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) β€” 15 ns
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (5.0 V nominal)
User I/O Pins β€” 212
Process Technology β€” CMOS EEPROM
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Operating Temperature (Commercial) β€” 0C to +70C
Architecture β€” Multiple Array MatriX (MAX) - 3rd generation
Boundary Scan β€” IEEE Std. 1149.1 JTAG
Programming Technology β€” EEPROM (non-volatile, reprogrammable)
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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