EPM9560RC304-20N vs EPM9560RC304-15F Comparison

Detailed side-by-side comparison of EPM9560RC304-20N by Altera and EPM9560RC304-15F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC304-20N EPM9560RC304-15F
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $18.75
Device Family MAX 9000 (EPM9560) MAX 9000
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) β€”
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 20 16 (40 macrocells each)
User I/O Pins 212 212
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) β€”
Maximum System Frequency 100 MHz β€”
Core Supply Voltage 5.0 V 5.0 V
I/O Voltage Support 3.3 V or 5.0 V configurable β€”
Configuration Technology EEPROM (non-volatile, in-system programmable) β€”
Programming Interface IEEE Std. 1149.1 JTAG (ISP) β€”
Package 304-pin RQFP (PowerQuad) RQFP-304 (304-pin Plastic QFP)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range [DATA_NEEDED: operating temperature range] β€”
RoHS Status RoHS3 Compliant [DATA_NEEDED: rohs status - not stated in source]
Moisture Sensitivity Level (MSL) 3 (168 Hours) β€”
Manufacturer Standard Lead Time 1-7 Days (distributor listing) β€”
Series β€” EPM9560
Propagation Delay (tpd) β€” 16.6 ns (max)
Maximum Internal Frequency β€” 117.6 MHz
Dedicated Inputs β€” 4
Programming Technology β€” 5.0 V in-system EEPROM via JTAG (IEEE 1149.1)
Architecture β€” Multiple Array MatriX (MAX) with PIA interconnect
Boundary Scan Test (BST) β€” Yes, JTAG-compliant
Operating Temperature β€” -40C to +85C (industrial)
Process Technology β€” High-performance CMOS, EEPROM-based
MSL Level β€” 3 (168 hours)

Datasheets & Resources

Browse All Products Create BOM Request Quote