EPM9560RCRC304-15 vs EPM9560RC304-2 Comparison
Detailed side-by-side comparison of EPM9560RCRC304-15 by Altera and EPM9560RC304-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteSpecification Comparison
| Parameter | EPM9560RCRC304-15 | EPM9560RC304-2 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $55.00 |
| Device Family | MAX 9000 (EPM9560) | β |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Macro Cells | 560 | β |
| Usable Gates | 12,000 | Approximately 12,000 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | β |
| Maximum Frequency | 117.6 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | On-chip EEPROM (non-volatile) |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG | β |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | β |
| Package | 304-pin RQFP (PowerQuad Flat Pack) | 304-pin RQFP (RC) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Number of User I/O Pins | [DATA_NEEDED: user I/O pin count] | β |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead Finish | [DATA_NEEDED: lead finish] | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (EPLD - Erasable PLD) |
| Macrocells | β | [DATA_NEEDED: macrocell count] |
| User I/O Pins | β | 304 |
| Speed Grade | β | -2 |
| Core Supply Voltage | β | 5.0 V |
| I/O Supply Voltage | β | 5.0 V |
| Programming Technology | β | EEPROM (in-system programmable) |
| JTAG Support | β | IEEE Std. 1149.1 (boundary-scan + ISP) |
| Operating Temperature | β | Commercial (0C to +70C) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |