EPM9560RI208-10 vs EPM9560RI208-15 Comparison
Detailed side-by-side comparison of EPM9560RI208-10 by Intel and EPM9560RI208-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-10 | EPM9560RI208-15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $67.80 | $20.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 12,000 | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency | 144 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | β |
| User I/O Pins | 212 (typical for 208-RQFP package) | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40 Β°C to +85 Β°C (Industrial) | 0 Β°C to 70 Β°C (industrial grade; per package suffix R) |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP | β |
| Configuration Memory | EEPROM, 100 erase/program cycles | On-chip EEPROM (non-volatile) |
| RoHS Status | ROHS3 Compliant | ROHS3 Compliant |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | 3 (168 hours) |
| Lead Time | 1-7 days (per fpgalink listing) | β |
| Architecture | β | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Typical Usable Gates | β | 12,000 |
| User I/Os | β | 153 |
| Internal Frequency (max) | β | 145 MHz |
| Propagation Delay (tPD) | β | 11.4 ns (commercial); 15 ns speed grade |
| Logic Family | β | CMOS |
| Number of Pins | β | 208 |
| Package Code | β | HFQFP (Power Quad Flat Pack, gull-wing) |
| Package Type | β | RQFP-208 |
| Supply Voltage (VCC) | β | 5 V nominal (4.5 V to 5.5 V) |
| I/O Voltage Support | β | 3.3 V or 5 V multi-volt I/O |
| In-System Programmability | β | Yes (JTAG / IEEE 1149.1) |
| Boundary-Scan (JTAG) | β | Compliant |