EPM9560RI208-15 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RI208-15 by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-15 | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $20.10 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 | β |
| Typical Usable Gates | 12,000 | β |
| User I/Os | 153 | β |
| Internal Frequency (max) | 145 MHz | β |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | β |
| Logic Family | CMOS | β |
| Number of Pins | 208 | β |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | β |
| Package Type | RQFP-208 | β |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | β |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | β |
| Operating Temperature | 0 Β°C to 70 Β°C (industrial grade; per package suffix R) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | Compliant | β |
| Configuration Memory | On-chip EEPROM (non-volatile) | β |
| RoHS Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | 3 (168 hours) | β |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | β | 12,000 gates |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| Package | β | 208-pin RQFP (Power Quad Flat Pack) |
| Mounting Type | β | Surface Mount |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |