EPM9560RI208-20 vs EPM9560R1208-20 Comparison

Detailed side-by-side comparison of EPM9560RI208-20 by Intel and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RI208-20 EPM9560R1208-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.10 $22.40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Usable Gates 12,000 6,000
Macro Cells 560 β€”
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 212 β€”
Pin-to-Pin Propagation Delay (tPD) 20 ns β€”
Counter Frequency (fCNT) 100 MHz β€”
Supply Voltage (VCC) 5.0 V β€”
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (IEEE 1149.1 JTAG)
Package 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm R-1208 (BGA-style fine-pitch)
Operating Temperature [DATA_NEEDED: operating temperature range grade] 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirm via current distributor data]
Mounting Type Surface Mount Surface Mount
Macrocells β€” 560
Logic Array Blocks β€” 52 (typical for 560 macrocells)
Maximum User I/O β€” 212
Propagation Delay (tPD) β€” 20 ns
Maximum Frequency (fMAX) β€” 125 MHz
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
Technology β€” CMOS EEPROM
Boundary-Scan Test β€” JTAG IEEE Std. 1149.1
Configuration Memory β€” On-chip EEPROM (non-volatile)

Datasheets & Resources

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