EPM9560RI208-20N vs EPM9560RI208-10N Comparison

Detailed side-by-side comparison of EPM9560RI208-20N by Intel and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RI208-20N

EPM9560RI208-20N - MAX 9000 CPLD 12K Gates 208-RQFP | Intel

EPM9560RI208-20N Obsolete
Altera
EPM9560RI208-10N

EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP

EPM9560RI208-10N Obsolete

Specification Comparison

Parameter EPM9560RI208-20N EPM9560RI208-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $61.75
Device Family MAX 9000 β€”
Usable Gates 12,000 12,000
Macrocells 560 β€”
Pin-to-Pin Delay 20 ns (-20 speed grade) 10 ns (speed grade -10)
Counter Speed 100 MHz β€”
Supply Voltage 5.0 V 5 V
Configuration Technology EEPROM (non-volatile) β€”
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG β€”
Package 208-pin RQFP 208-pin RQFP (PQFP)
Mounting Type Surface Mount β€”
Operating Temperature Industrial (-40C to +85C) -40C to +85C (Industrial grade, "RI" suffix)
Development Tool MAX+PLUS II β€”
Design Entry Schematic, VHDL, Verilog HDL, AHDL β€”
RoHS Status [DATA_NEEDED: RoHS status] ROHS3 Compliant (per fpgalink)
Packaging Tray β€”
Logic Architecture Third-generation MAX (Multiple Array MatriX) β€”
Fabrication Process Advanced CMOS β€”
Family β€” MAX 9000
Device Type β€” CPLD (Complex Programmable Logic Device)
Architecture β€” CMOS EEPROM-based Multiple Array MatriX (MAX)
Macro Cells β€” 560
Register Bits β€” 12,160
User I/Os β€” 212
Maximum Frequency β€” 100 MHz to 125 MHz
Programming Method β€” In-system via IEEE 1149.1 (JTAG)
MSL Level β€” 3 (168 Hours)
Configuration Memory β€” On-chip EEPROM (non-volatile)

Datasheets & Resources

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