EPM9560RI208-20N vs EPM9560TC208-20 Comparison
Detailed side-by-side comparison of EPM9560RI208-20N by Intel and EPM9560TC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-20N | EPM9560TC208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $60.00 |
| Device Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | 12000 |
| Macrocells | 560 | 560 |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | β |
| Counter Speed | 100 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP | TQFP-208 (TC208) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | Industrial (-40C to +85C) | [DATA_NEEDED: commercial/industrial temperature grade] |
| Development Tool | MAX+PLUS II | β |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Packaging | Tray | β |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | β |
| Fabrication Process | Advanced CMOS | β |
| User I/O | β | 149 |
| Propagation Delay (tPD) | β | 20 ns |
| Speed Grade | β | -20 |
| Pin/Package Code | β | TC208 (JEDEC S-PQFP-G208) |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |
| Technology | β | CMOS EEPROM |
| Core Supply Voltage | β | 5 V |
| I/O Supply Voltage (MultiVolt) | β | 3.3 V or 5 V |
| In-System Programming | β | Yes (IEEE Std 1149.1 JTAG) |
| Flip-Flops | β | 772 |