EPM9560RI208-20W vs EPM9560RI208-10N Comparison

Detailed side-by-side comparison of EPM9560RI208-20W by Intel and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RI208-20W

EPM9560RI208-20W - MAX 9000 CPLD, 12K Gates, 208-Pin | Intel

EPM9560RI208-20W Nrnd
Altera
EPM9560RI208-10N

EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP

EPM9560RI208-10N Obsolete

Specification Comparison

Parameter EPM9560RI208-20W EPM9560RI208-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $48.75 $61.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 12,000
Macrocells 560 β€”
Logic Array Blocks (LABs) 16 LABs of 40 macrocells each β€”
User I/O Pins 212 β€”
Pin-to-Pin Delay (tPD) 20 ns β€”
Counter Frequency (fCNT) 100 MHz β€”
Speed Grade -20 β€”
Supply Voltage 5.0 V 5 V
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Programming Technology CMOS EEPROM β€”
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PQFP)
Operating Temperature -40C to +85C (Industrial) -40C to +85C (Industrial grade, "RI" suffix)
Architecture Third-generation Multiple Array MatriX (MAX) CMOS EEPROM-based Multiple Array MatriX (MAX)
Macro Cells β€” 560
Register Bits β€” 12,160
User I/Os β€” 212
Pin-to-Pin Delay β€” 10 ns (speed grade -10)
Maximum Frequency β€” 100 MHz to 125 MHz
Programming Method β€” In-system via IEEE 1149.1 (JTAG)
MSL Level β€” 3 (168 Hours)
RoHS Status β€” ROHS3 Compliant (per fpgalink)
Configuration Memory β€” On-chip EEPROM (non-volatile)

Datasheets & Resources

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