EPM9560RI210-15 vs EPM9560RC208-15 Comparison

Detailed side-by-side comparison of EPM9560RI210-15 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RI210-15 EPM9560RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Family MAX 9000 (EPM9560) MAX 9000
Device Type Complex Programmable Logic Device (CPLD) EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells 560 β€”
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 20 β€”
User I/O Pins 164 β€”
Pin-to-Pin Delay (tPD) 15 ns (-15 speed grade) β€”
Supply Voltage (VCCINT) 5.0 V β€”
I/O Voltage (MultiVolt) 3.3 V / 5.0 V compatible β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (JTAG ISP) Yes, via IEEE Std. 1149.1 JTAG
JTAG Boundary Scan IEEE 1149.1 compliant β€”
Package 210-pin RQFP (PowerQuad) 208-pin RQFP (Power Quad Flat Pack)
Operating Temperature Industrial (-40C to +85C) [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount Surface Mount
RoHS Status ROHS3 Compliant [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level (MSL) 3 (168 Hours) β€”
Manufacturer Standard Lead Time 1-7 Days (distributor stock) β€”
Macro Cells β€” 560 macro cells
Pin-to-Pin Delay β€” 15 ns
Counter Speed β€” 117.6 MHz
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile)
Number of I/O Pins β€” [DATA_NEEDED: number of I/O pins]
Logic Array Blocks β€” [DATA_NEEDED: number of logic array blocks]
Speed Grade β€” -15 (15 ns pin-to-pin)
Architecture β€” Third-generation Multiple Array MatriX (MAX)

Datasheets & Resources

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