EPM9560RI304-15 vs EPM9560RC304-15 Comparison

Detailed side-by-side comparison of EPM9560RI304-15 by Intel and EPM9560RC304-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RI304-15

EPM9560RI304-15 - 560-Macrocell MAX 9000 CPLD | Intel/Altera | 15ns

EPM9560RI304-15 Nrnd
Altera
EPM9560RC304-15

EPM9560RC304-15 - 560-Macrocell MAX CPLD, 15ns | Altera / Intel

EPM9560RC304-15 Obsolete

Specification Comparison

Parameter EPM9560RI304-15 EPM9560RC304-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $112.00 $9.40
Device Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX) - EEPROM-based CPLD Multiple Array MatriX (MAX), EEPROM-based
Macrocells 560 560
Flip-Flops 772 β€”
User I/Os 212 (216 per some datasheets) β€”
Dedicated Inputs 4 β€”
Total Terminals 304 β€”
Package Code HFQFP / S-PQFP-G304 β€”
Package Type 304-pin RQFP (Quad Flat Pack, gull-wing) β€”
Propagation Delay (tpd) 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA β€”
Maximum Internal Frequency 145 MHz β€”
Speed Grade -15 β€”
Supply Voltage (VCCINT/VCCIO) 4.5 V to 5.5 V (5 V typical) β€”
I/O Logic Levels 3.3 V or 5 V configurable β€”
Operating Temperature 0 C to 70 C (commercial) [DATA_NEEDED: industrial/commercial temperature grade]
Temperature Grade Industrial (per Partstack listings) β€”
Logic Family CMOS β€”
Programming 5.0-V in-system programmable via JTAG (IEEE 1149.1) β€”
Process Technology 0.5 Β΅m CMOS EEPROM β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: lead-free / RoHS compliance status]
Logic Array Blocks (LABs) β€” 16
User I/O Pins β€” 212 (maximum)
Propagation Delay (tPD) β€” 15 ns (combinatorial, pin-to-pin)
Pin Count β€” 304
Package β€” 304-pin RQFP (Plastic Quad Flat Pack)
Supply Voltage (VCCINT) β€” 5.0 V
I/O Standard β€” 5.0 V TTL / PCI-compliant
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Configuration Memory β€” On-chip EEPROM (non-volatile)
Technology Node β€” High-performance CMOS, EEPROM process

Datasheets & Resources

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