EPM9560RI304-20N vs EPM9560RI304-15N Comparison

Detailed side-by-side comparison of EPM9560RI304-20N by Intel and EPM9560RI304-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RI304-20N EPM9560RI304-15N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $58.40 $88.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (EE PLD), in-system programmable, EEPROM-based
Macrocells 560 560
Usable Gates 12,000 β€”
Logic Array Blocks (LABs) 35 16
Maximum User I/O Pins 212 β€”
Pin-to-Pin Propagation Delay (tPD) 20 ns β€”
Internal Performance Grade 100 MHz β€”
Supply Voltage (VCCINT/VCCIO) 5.0 V β€”
Process Technology CMOS EEPROM-based High-performance CMOS, EEPROM configuration memory
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) β€”
Package 304-pin RQFP (Plastic Quad Flat Pack) RQFP-304 (HFQFP-304), 1.27 mm gull-wing pitch
Mounting Type Surface Mount β€”
Operating Temperature -40C to +85C (industrial; verify per lot) β€”
RoHS Status Unknown (legacy Altera part - confirm per lot) β€”
Series / Part Number β€” EPM9560
Flip-Flops β€” 772
User I/Os β€” 216
Maximum Internal Frequency β€” 145 MHz
Propagation Delay (pin-to-pin) β€” 15 ns (speed grade -15)
Supply Voltage β€” 5.0 V core, multi-volt I/O (3.3 V / 5.0 V)
Pin Count β€” 304
Operating Temperature (commercial) β€” 0 C to 70 C
Programming Interface β€” JTAG (IEEE 1532 / IEEE 1149.1) in-system programmable
Architecture β€” Multiple Array MatriX (MAX), third-generation, PIA interconnect
Lead-Free / RoHS β€” [DATA_NEEDED: lead-free / RoHS status of EPM9560RI304-15N]

Datasheets & Resources

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