EPM9560RI304 vs EPM9560RC304-10 Comparison
Detailed side-by-side comparison of EPM9560RI304 by Altera and EPM9560RC304-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RI304
EPM9560RI304 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera
EPM9560RI304 ObsoleteIntel
EPM9560RC304-10
EPM9560RC304-10 - MAX 9000 CPLD, 560 Logic Elements | Intel
EPM9560RC304-10 NrndSpecification Comparison
| Parameter | EPM9560RI304 | EPM9560RC304-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $17.60 |
| Device Family | MAX 9000 | β |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 16000 |
| Maximum User I/O Pins | 216 | β |
| Propagation Delay (tPD) | 20 ns | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| JTAG Interface | IEEE Std. 1149.1 (JTAG) | β |
| Package | 304-pin BFQFP/RQFP (HFQFP) | RQFP-304 (RC) |
| Package Code | HFQFP, square | β |
| Terminal Form | Gull wing | β |
| Number of Terminals | 304 | β |
| Operating Temperature Grade | Industrial (-40C to +85C) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD / EPLD |
| Logic Elements | β | 560 |
| Pin Count | β | 304 |
| Pin-to-Pin Propagation Delay | β | 12 ns |
| Speed Grade | β | -10 |
| Supply Voltage | β | 5 V |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| User I/O Pins | β | 304 (package-limited) |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Programming Method | β | JTAG in-system (ISP) |
| Process Technology | β | 0.65 Β΅m CMOS EEPROM |
| MSL Level | β | 3 (168 Hours) |