EPM9560TC208-20 vs EPM9560RI208-20N Comparison

Detailed side-by-side comparison of EPM9560TC208-20 by Altera and EPM9560RI208-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560TC208-20

EPM9560TC208-20 - MAX 9000 CPLD, 560 Macrocells, TQFP-208 | Altera

EPM9560TC208-20 Obsolete
Intel
EPM9560RI208-20N

EPM9560RI208-20N - MAX 9000 CPLD 12K Gates 208-RQFP | Intel

EPM9560RI208-20N Obsolete

Specification Comparison

Parameter EPM9560TC208-20 EPM9560RI208-20N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $60.00 $0.00
Device Family MAX 9000 MAX 9000
Macrocells 560 560
Usable Gates 12000 12,000
User I/O 149 β€”
Propagation Delay (tPD) 20 ns β€”
Speed Grade -20 β€”
Package TQFP-208 (TC208) 208-pin RQFP
Pin/Package Code TC208 (JEDEC S-PQFP-G208) β€”
Architecture Multiple Array MatriX (MAX) - third generation β€”
Technology CMOS EEPROM β€”
Core Supply Voltage 5 V β€”
I/O Supply Voltage (MultiVolt) 3.3 V or 5 V β€”
In-System Programming Yes (IEEE Std 1149.1 JTAG) β€”
Flip-Flops 772 β€”
Operating Temperature [DATA_NEEDED: commercial/industrial temperature grade] Industrial (-40C to +85C)
Mounting Type Surface Mount Surface Mount
RoHS Status unknown [DATA_NEEDED: RoHS status]
Pin-to-Pin Delay β€” 20 ns (-20 speed grade)
Counter Speed β€” 100 MHz
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Development Tool β€” MAX+PLUS II
Design Entry β€” Schematic, VHDL, Verilog HDL, AHDL
Packaging β€” Tray
Logic Architecture β€” Third-generation MAX (Multiple Array MatriX)
Fabrication Process β€” Advanced CMOS

Datasheets & Resources

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