EPM9560WC208-15 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-15 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $105.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Technology | CMOS | β |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 35 | β |
| Flip-Flops | 772 | β |
| User I/O Pins (max) | 149 | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Propagation Delay (tPD) | 16.6 ns | β |
| Speed Grade | -15 | -15 (15 ns pin-to-pin) |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | β |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | β |
| RoHS Status | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS status] |
| Usable Gates | β | 12,000 gates |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |