EPM9560WC208-15C vs EPM9560RC208-15 Comparison

Detailed side-by-side comparison of EPM9560WC208-15C by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560WC208-15C EPM9560RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $178.00 $0.00
Device Family MAX 9000 β€”
Series EPM9560 β€”
Macrocells 560 β€”
Logic Array Blocks (LABs) 35 β€”
Flip-Flops 772 β€”
User I/O Pins 149 β€”
Supply Voltage 3.3 V or 5 V 5.0 V
Maximum Clock Frequency 117.6 MHz β€”
Pin-to-Pin Propagation Delay (tPD) 16.6 ns β€”
Process Technology 0.35 Β΅m CMOS EEPROM β€”
Package CQFP-208 (Ceramic Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Terminal Pitch 0.50 mm β€”
Mounting Type Surface Mount Surface Mount
Programming Interface IEEE 1149.1 JTAG β€”
Operating Temperature Grade C (Commercial) β€”
MultiVolt I/O Yes (3.3 V / 5 V tolerant) β€”
RoHS Status ROHS3 Compliant [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level (MSL) 3 (168 Hours) β€”
Family β€” MAX 9000
Device Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Usable Gates β€” 12,000 gates
Macro Cells β€” 560 macro cells
Pin-to-Pin Delay β€” 15 ns
Counter Speed β€” 117.6 MHz
Configuration Technology β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Operating Temperature β€” [DATA_NEEDED: operating temperature range]
Number of I/O Pins β€” [DATA_NEEDED: number of I/O pins]
Logic Array Blocks β€” [DATA_NEEDED: number of logic array blocks]
Speed Grade β€” -15 (15 ns pin-to-pin)
Architecture β€” Third-generation Multiple Array MatriX (MAX)

Datasheets & Resources

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