EPM9560WC208 vs EPM9560ARC208-10 Comparison
Detailed side-by-side comparison of EPM9560WC208 by Altera and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208
EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
EPM9560WC208 NrndIntel
EPM9560ARC208-10
EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel
EPM9560ARC208-10 ObsoleteSpecification Comparison
| Parameter | EPM9560WC208 | EPM9560ARC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | EE Programmable Logic Device (CPLD) | β |
| Macrocells | 560 | 560 macrocells |
| Logic Array Blocks (LABs) | 35 | β |
| Flip-Flops | 772 | β |
| Maximum User I/O | 149 | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Propagation Delay (tpd, -15 grade) | 16.6 ns | β |
| Supply Voltage | 3.3 V or 5 V | 5.0 V |
| Process Technology | CMOS, electrically erasable | β |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Terminal Pitch | 0.50 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | β |
| Configuration Memory | Non-volatile EE (instant-on) | β |
| Hot Socketing Support | Yes | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Family | β | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 12,000 gates |
| Logic Array Blocks | β | 35 LABs |
| User I/O Pins | β | 153 I/O |
| Propagation Delay (tPD) | β | 10 ns (speed grade -10) |
| Internal Frequency | β | 144.9 MHz |
| Logic Family | β | CMOS |
| Configuration Technology | β | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | β | IEEE 1149.1 boundary-scan (ISP) |
| Operating Temperature | β | 0 C to +70 C (commercial) |
| Pin Count | β | 208 pins |