EPM9560WC208 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560WC208 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208
EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
EPM9560WC208 NrndAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9560WC208 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 35 | β |
| Flip-Flops | 772 | β |
| Maximum User I/O | 149 | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Propagation Delay (tpd, -15 grade) | 16.6 ns | β |
| Supply Voltage | 3.3 V or 5 V | 5.0 V |
| Process Technology | CMOS, electrically erasable | β |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | β |
| Configuration Memory | Non-volatile EE (instant-on) | β |
| Hot Socketing Support | Yes | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Usable Gates | β | 12,000 gates |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |