XC3090L-125PC84C vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of XC3090L-125PC84C by Xilinx and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-125PC84C
XC3090L-125PC84C - 5K-Gate FPGA, 125MHz, 84-Pin PLCC | Xilinx
XC3090L-125PC84C ObsoleteIntel
EPM9560RC208-20
EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel
EPM9560RC208-20 ObsoleteSpecification Comparison
| Parameter | XC3090L-125PC84C | EPM9560RC208-20 |
|---|---|---|
| Brand | Xilinx | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $64.00 | $0.00 |
| Manufacturer | Xilinx | β |
| Series | XC3000L | β |
| Product Type | Field Programmable Gate Array (FPGA) | β |
| Logic Family | XC3000L Low-Voltage Logic Cell Array | β |
| Process Technology | CMOS, SRAM-based | β |
| Configurable Logic Blocks (CLBs) | 320 | β |
| Equivalent Gates | ~5,000 | β |
| Flip-Flops | 928 | 772 |
| Maximum Toggle Frequency | 125 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) | β |
| Operating Temperature | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Package | 84-pin PLCC (J-lead, package code QCCJ) | 208-pin RQFP (28x28 mm) |
| Terminal Form | J-BEND (J-lead) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Interface | Serial/parallel mode, JTAG (IEEE 1149.1) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Family | β | MAX 9000 (EPM9560) |
| Macrocells | β | 560 |
| Usable Gates | β | 12,000 |
| Logic Array Blocks | β | 35 |
| User I/O Pins | β | 153 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Clock Frequency | β | 100 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| I/O Standards | β | 5.0 V TTL/CMOS compatible |
| MSL Level | β | [DATA_NEEDED: MSL level] |