XC3090L-125PC84C vs XC3090L-8PCG84C Comparison
Detailed side-by-side comparison of XC3090L-125PC84C by Xilinx and XC3090L-8PCG84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-125PC84C
XC3090L-125PC84C - 5K-Gate FPGA, 125MHz, 84-Pin PLCC | Xilinx
XC3090L-125PC84C ObsoleteXilinx
XC3090L-8PCG84C
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C β Last Time BuySpecification Comparison
| Parameter | XC3090L-125PC84C | XC3090L-8PCG84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $64.00 | $26.10 |
| Manufacturer | Xilinx | β |
| Series | XC3000L | β |
| Product Type | Field Programmable Gate Array (FPGA) | β |
| Logic Family | XC3000L Low-Voltage Logic Cell Array | β |
| Process Technology | CMOS, SRAM-based | [DATA_NEEDED: process node] |
| Configurable Logic Blocks (CLBs) | 320 | β |
| Equivalent Gates | ~5,000 | β |
| Flip-Flops | 928 | β |
| Maximum Toggle Frequency | 125 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Operating Temperature | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] | 0 C to +70 C (commercial 'C' suffix) |
| Package | 84-pin PLCC (J-lead, package code QCCJ) | 84-pin PLCC (J-Lead, PCG84) |
| Terminal Form | J-BEND (J-lead) | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC J-Lead) |
| Configuration Interface | Serial/parallel mode, JTAG (IEEE 1149.1) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Family | β | XC3000A/L Series FPGA |
| Logic Cells / CLBs | β | 70 Configurable Logic Blocks |
| Gate Count | β | 6,400 gates (typical) |
| Configuration Program Store | β | 64,160 bits |
| User I/O Pins | β | 70 (maximum) |
| Speed Grade | β | -8 (moderate) |
| Configuration Modes | β | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Configuration Clock Range | β | [DATA_NEEDED: CCLK frequency range] |
| Lead-Free | β | unknown |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Programming Technology | β | SRAM-based, in-system reconfigurable |