XC3090L-7TQG176I vs XC3090L-7TQG176C Comparison
Detailed side-by-side comparison of XC3090L-7TQG176I by Xilinx and XC3090L-7TQG176C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-7TQG176I - 3200 Gates FPGA, 176-pin TQG, -40C to +100C | Xilinx
XC3090L-7TQG176I Obsolete
Specification Comparison
| Parameter | XC3090L-7TQG176I | XC3090L-7TQG176C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $64.80 | $21.20 |
| Series | XC3000L (Low-Voltage) | β |
| Family | XC3000L Field Programmable Gate Array | XC3000L |
| Usable Gates | 3200 | 5,000 (typical, up to 9,000 peak) |
| Configurable Logic Blocks (CLBs) | 100 | β |
| Flip-Flops | 144 | β |
| Maximum User I/O | 176 | β |
| Logic Cells | [DATA_NEEDED: logic cell count] | β |
| Core Supply Voltage (Vcc) | 3.0 V to 3.6 V (3.3 V typical) | β |
| I/O Supply Voltage (Vcco) | 3.3 V or 5.0 V tolerant | β |
| Process Technology | 0.6 um CMOS SRAM | 0.8 micron CMOS |
| Speed Grade | -7 | β |
| Temperature Grade (I) | -40C to +100C (Industrial) | β |
| Package | TQG-176 (Thin Quad Gulp, 176-pin) | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Interface | JTAG (IEEE 1149.1) + XACT parallel | β |
| On-chip RAM | Distributed SelectRAM | β |
| RoHS Status | Compliant | unknown |
| Lead-Free | Yes | β |
| Device | β | XC3090L |
| Logic Cells / CLBs | β | 100 CLBs (320 F-FFs) |
| User I/O Count | β | 144 (maximum, TQG176) |
| Configuration Memory | β | SRAM (volatile, requires external PROM) |
| Supply Voltage (Core) | β | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | β | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | β | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Operating Temperature Range | β | 0C to +85C (C suffix, commercial) |
| Configuration Mode | β | Serial (master/slave) and JTAG (IEEE 1149.1) |
| MSL Level | β | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | β | [DATA_NEEDED] |
| Configuration Clock Source | β | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | β | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |