XC3090L-8PCG84C vs XC3090L-125PC84C Comparison
Detailed side-by-side comparison of XC3090L-8PCG84C by Xilinx and XC3090L-125PC84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | XC3090L-8PCG84C | XC3090L-125PC84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $26.10 | $64.00 |
| Family | XC3000A/L Series FPGA | β |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | β |
| Gate Count | 6,400 gates (typical) | β |
| Configuration Program Store | 64,160 bits | β |
| User I/O Pins | 70 (maximum) | β |
| Package | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-lead, package code QCCJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | 3.0 V to 3.6 V (typical 3.3 V) |
| Speed Grade | -8 (moderate) | β |
| Operating Temperature | 0 C to +70 C (commercial 'C' suffix) | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | β |
| Process Technology | [DATA_NEEDED: process node] | CMOS, SRAM-based |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | β |
| Mounting Type | Surface Mount (PLCC J-Lead) | Surface Mount |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Technology | SRAM-based, in-system reconfigurable | β |
| Manufacturer | β | Xilinx |
| Series | β | XC3000L |
| Product Type | β | Field Programmable Gate Array (FPGA) |
| Logic Family | β | XC3000L Low-Voltage Logic Cell Array |
| Configurable Logic Blocks (CLBs) | β | 320 |
| Equivalent Gates | β | ~5,000 |
| Flip-Flops | β | 928 |
| Maximum Toggle Frequency | β | 125 MHz |
| Terminal Form | β | J-BEND (J-lead) |
| Configuration Interface | β | Serial/parallel mode, JTAG (IEEE 1149.1) |