XC3090L-8PCG84C vs XC3090LTM-8PC84C Comparison
Detailed side-by-side comparison of XC3090L-8PCG84C by Xilinx and XC3090LTM-8PC84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-8PCG84C
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C β Last Time BuyXilinx
XC3090LTM-8PC84C
XC3090LTM-8PC84C - XC3000L FPGA, 6K Gates, 84-PLCC | Xilinx
XC3090LTM-8PC84C ObsoleteSpecification Comparison
| Parameter | XC3090L-8PCG84C | XC3090LTM-8PC84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $26.10 | $43.25 |
| Family | XC3000A/L Series FPGA | XC3000L Low Voltage Logic Cell Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | β |
| Gate Count | 6,400 gates (typical) | β |
| Configuration Program Store | 64,160 bits | β |
| User I/O Pins | 70 (maximum) | β |
| Package | 84-pin PLCC (J-Lead, PCG84) | 84-Pin Plastic Leaded Chip Carrier (PLCC, J-Lead) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | β |
| Speed Grade | -8 (moderate) | -8 (per suffix; see device decoder) |
| Operating Temperature | 0 C to +70 C (commercial 'C' suffix) | -40 C to +85 C (industrial, TM suffix typically commercial/industrial) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | β |
| Process Technology | [DATA_NEEDED: process node] | 0.8 um CMOS SRAM-based |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | β |
| Mounting Type | Surface Mount (PLCC J-Lead) | Surface Mount (PLCC socket-compatible) |
| RoHS Status | unknown | unknown |
| Lead-Free | unknown | unknown |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Technology | SRAM-based, in-system reconfigurable | β |
| Logic Cells / Gates | β | ~6,000 usable gates |
| Configurable Logic Blocks (CLBs) | β | 320 |
| Configuration Memory | β | 64,160 bits (distributed SRAM) |
| Configuration Method | β | External EEPROM/EPROM/ROM/master/microprocessor mode |
| Core Supply Voltage | β | 3.0 V to 3.6 V (3.3 V typical) |
| Pin Count | β | 84 |
| Maximum Toggle Frequency | β | [DATA_NEEDED: specific fmax value] |
| Logic Block Delays | β | [DATA_NEEDED: typical TBU/TPIO delay] |
| I/O Standard Support | β | TTL/CMOS 3.3 V (5 V tolerant with restrictions) |
| Programming Toolchain | β | XACT / Foundation (legacy, EOL software) |