XC3090LTM-8PC84C vs XC3090L-8PCG84C Comparison
Detailed side-by-side comparison of XC3090LTM-8PC84C by Xilinx and XC3090L-8PCG84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090LTM-8PC84C
XC3090LTM-8PC84C - XC3000L FPGA, 6K Gates, 84-PLCC | Xilinx
XC3090LTM-8PC84C ObsoleteXilinx
XC3090L-8PCG84C
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C β Last Time BuySpecification Comparison
| Parameter | XC3090LTM-8PC84C | XC3090L-8PCG84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $43.25 | $26.10 |
| Family | XC3000L Low Voltage Logic Cell Array | XC3000A/L Series FPGA |
| Logic Cells / Gates | ~6,000 usable gates | β |
| Configurable Logic Blocks (CLBs) | 320 | β |
| Configuration Memory | 64,160 bits (distributed SRAM) | β |
| Configuration Method | External EEPROM/EPROM/ROM/master/microprocessor mode | β |
| Core Supply Voltage | 3.0 V to 3.6 V (3.3 V typical) | β |
| Process Technology | 0.8 um CMOS SRAM-based | [DATA_NEEDED: process node] |
| Package | 84-Pin Plastic Leaded Chip Carrier (PLCC, J-Lead) | 84-pin PLCC (J-Lead, PCG84) |
| Pin Count | 84 | β |
| Mounting Type | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC J-Lead) |
| Speed Grade | -8 (per suffix; see device decoder) | -8 (moderate) |
| Operating Temperature | -40 C to +85 C (industrial, TM suffix typically commercial/industrial) | 0 C to +70 C (commercial 'C' suffix) |
| Maximum Toggle Frequency | [DATA_NEEDED: specific fmax value] | β |
| Logic Block Delays | [DATA_NEEDED: typical TBU/TPIO delay] | β |
| I/O Standard Support | TTL/CMOS 3.3 V (5 V tolerant with restrictions) | β |
| RoHS Status | unknown | unknown |
| Lead-Free | unknown | unknown |
| Programming Toolchain | XACT / Foundation (legacy, EOL software) | β |
| Logic Cells / CLBs | β | 70 Configurable Logic Blocks |
| Gate Count | β | 6,400 gates (typical) |
| Configuration Program Store | β | 64,160 bits |
| User I/O Pins | β | 70 (maximum) |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | β | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Configuration Clock Range | β | [DATA_NEEDED: CCLK frequency range] |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Programming Technology | β | SRAM-based, in-system reconfigurable |