SN74LVC1G125DBVR - 3-State Bus Buffer SOT-23-5 | TI
MPN: SN74LVC1G125DBVR β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.41 | $0.41 |
| 10 | $0.33 | $3.30 |
| 100 | $0.19 | $19.00 |
| 500 | $0.13 | $65.00 |
| 1,000 | $0.1 | $100.00 |
Drop-in alternatives for SN74LVC1G125DBVR β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
SN74LVC1G126DBVR
β Drop-Inπ Reference alternative (not in catalog)
SN74AHCT1G125DBVR
β Drop-Inπ Reference alternative (not in catalog)
74LVC1G125DBV,125
β Drop-Inπ Reference alternative (not in catalog)
NC7SZ125P6X
β Drop-Inπ Reference alternative (not in catalog)
M74VHC1G125DFT1G
β Drop-Inπ Reference alternative (not in catalog)
SN74LVC1G125DBVR Maximum Ratings & Electrical Characteristics
| Logic Function | Non-inverting buffer with 3-state output |
| Supply Voltage Range | 1.65 V to 5.5 V |
| Input Voltage Range | Up to 5.5 V (overvoltage tolerant) |
| Output Drive Current | +/-24 mA at 3.3 V |
| Max Propagation Delay (tpd) | Specified at 3.3 V |
| Max Quiescent Current (ICC) | 10 uA |
| Ioff Feature | Yes (partial-power-down support) |
| Output Enable | Active-low OE pin |
| Elements / Bits | 1 element, 1 bit per element |
| Output Type | 3-State |
| Operating Temperature | -40C to +125C |
| Package | SOT-23-5 (DBV) |
| Mounting Type | Surface Mount |
| MSL Level | 1 (260C unlimited) |
| RoHS Status | Compliant |
| Technology | LVC (Low-Voltage CMOS) |
SN74LVC1G125DBVR Pin Configuration
| Pin 1 | OE β Output enable (active-low; output disabled/high-Z when high) |
| Pin 2 | GND β Ground |
| Pin 3 | A β Data input |
| Pin 4 | Y β 3-state output |
| Pin 5 | VCC β Power supply, 1.65 V to 5.5 V |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
SN74LVC1G125DBVR is suitable for 6 applications: Logic Level Buffering (1.8V to 3.3V), Bus Isolation in Multi-Board Systems, Industrial Control Signal Conditioning, Battery-Powered Portable Devices, Communication Interface Buffering, Automotive Subsystem Logic Gating.
Logic Level Buffering (1.8V to 3.3V)
The SN74LVC1G125DBVR buffers low-voltage logic signals into higher-voltage domains thanks to its 1.65-V to 5.5-V supply range and 5.5-V tolerant inputs. A 1.8-V signal can drive the input while the device runs at 3.3 V, regenerating the signal with +/-24-mA drive capability. Placed inline on SPI, UART, or GPIO lines, it improves fanout and noise margin. The 3-state output lets the line be released when disabled, and the 10-uA max ICC keeps battery drain negligible in portable designs.
Recommended
Bus Isolation in Multi-Board Systems
In backplane and multi-board systems, the SN74LVC1G125DBVR isolates shared signal lines to prevent bus contention. The 3-state output enters high impedance when the active-low OE pin is driven high, releasing the bus so other masters can drive it. With a 50-pF rated capacitive load and +/-24-mA output drive at 3.3 V, one buffer can adequately drive a moderate bus segment. The Ioff partial-power-down feature allows boards to be unpowered while the bus remains live, preventing back-feed current damage.
Recommended
Industrial Control Signal Conditioning
Industrial PLC and motor-control boards operating at -40C to +125C benefit from the SN74LVC1G125DBVR's full industrial temperature range and robust CMOS noise immunity. It buffers sensor or controller output signals before they drive optocouplers, gate-driver inputs, or long PCB traces, where refreshed logic levels and 24-mA drive improve reliability. Pairing with TI isolation or CAN transceiver parts on the same board creates clean, isolated industrial interfaces tolerant of noisy power environments.
Recommended
Battery-Powered Portable Devices
With a maximum ICC of only 10 uA and MSL 1, 260C unlimited rating, the SN74LVC1G125DBVR suits battery-powered wearables and handheld instruments. The device occupies minimal board area in SOT-23-5 and supports partial-power-down via Ioff, letting subsystems sleep without loading active buses. Its wide 1.65-V to 5.5-V supply range allows operation directly from single-cell Li-Ion or 3-V coin cells across the full discharge curve, while +/-24-mA drive at 3.3 V still handles LED or interface loading when needed.
Recommended
Communication Interface Buffering
I2C, SPI, and UART lines benefit from a single-gate 3-state buffer such as the SN74LVC1G125DBVR for hot-swappable or shared interfaces. The active-low OE pin lets an MCU gate the line during boot or configuration, and the fast LVC family propagation delay (specified at 3.3 V) preserves signal timing on high-speed SPI clock lines up to tens of MHz. Driving up to 50 pF while meeting all datasheet specs covers typical trace and connector capacitance on interface headers.
Recommended
Automotive Subsystem Logic Gating
Automotive infotainment and body-control modules use 3-state buffers like the SN74LVC1G125DBVR for tri-stating diagnostic or configuration lines during fault conditions. The -40C to +125C operating range covers under-hood and cabin electronics environments, and the 5.5-V tolerant input survives automotive load-dump clamped rails. When AEC-Q100 qualification is mandatory, pair or substitute with TI's automotive-qualified logic family members and Q1-rated transceivers within the same design flow.
Recommended
Recommended Products Summary
Engineering reference data for SN74LVC1G125DBVR β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74LVC1G126DBVR | SN74AHCT1G125DBVR | 74LVC1G125DBV,125 | NC7SZ125P6X | M74VHC1G125DFT1G |
|---|---|---|---|---|---|---|
| Package | SOT-23-5 (DBV) | SOT-23-5 - same | SOT-23-5 - same | SOT-23-5 - same | SOT-23-5 - same | SOT-23-5 - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Nexperia | onsemi | onsemi |
| Supply Voltage Range | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 4.5 V to 5.5 V | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 2 V to 5.5 V |
| Output Enable Polarity | Active-low OE | Active-high OE | Active-low OE | Active-low OE | Active-low OE | Active-low OE |
| Output Drive | +/-24 mA at 3.3 V | +/-24 mA at 3.3 V | +/-8 mA at 4.5 V | +/-24 mA at 3.0 V | +/-24 mA at 3.0 V | [DATA_NEEDED] |
| Max ICC | 10 uA | 10 uA | [DATA_NEEDED] | 10 uA | [DATA_NEEDED] | [DATA_NEEDED] |
| Ioff Partial-Power-Down | Yes | Yes | No | Yes | Yes | [DATA_NEEDED] |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +85C | -55C to +125C |
| Approx Price (1 pc) | $0.41 (as of 2026-08-29) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Active-low OE control in LVC speed class (vs SN74LVC1G126DBVR)
- Ioff partial-power-down support (vs SN74AHCT1G125DBVR)
- Full -40C to +125C industrial range vs NC7SZ125 (vs NC7SZ125P6X)
- 5.5-V tolerant inputs at 3.3-V VCC (vs M74VHC1G125DFT1G)
Design Notes
Place a 0.1-uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 5) with a short return to GND (pin 2). Keep the A input trace short and away from clock lines to avoid coupling noise into the CMOS high-impedance input. Unused area under the SOT-23-5 can host a small ground pour to improve signal return paths.
Never leave the OE pin floating - tie it through a pull-down (typically 10 k-ohm) to the rail that guarantees the output is disabled (high) by default, then drive it low to enable. Floating CMOS inputs can oscillate and draw excess current. Also verify bus arbitration: if two 3-state buffers drive the same line simultaneously, contention currents through the Β±24-mA drivers can cause excessive dissipation and glitches.
Per TI datasheet, the device drives up to 50 pF while meeting all specifications. For capacitive loads above 50 pF (long cables, multiple loads), add a series resistor (22 to 50 ohms) between the Y output and the load to limit output current and damp reflections. At 5-V VCC with fast edges, this series termination also reduces overshoot and EMI on stub traces.
The Ioff feature protects the device when VCC is powered down, but the bus voltage applied to Y must stay within data-sheet absolute maximum limits. In multi-rail designs, sequence the buffer's VCC last or ensure the OE pin keeps the output tri-stated until VCC stabilizes, preventing partial-power glitches on shared buses.
Compliance Information
RoHS compliant and MSL 1 (260C unlimited) per distributor and PartGenie data. REACH and halogen-free status not stated in provided data.