EP1S25F780C5 vs EP1S25F780I6N Comparison
Detailed side-by-side comparison of EP1S25F780C5 by Altera and EP1S25F780I6N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP1S25F780C5 - Stratix I FPGA, 25,660 LEs, 597 I/O, 780-FBGA | Altera / Intel
EP1S25F780C5 β Last Time BuyIntel
EP1S25F780I6N - Stratix 25,660-LE FPGA, 780-BBGA, Industrial | Altera/Intel
EP1S25F780I6N ObsoleteSpecification Comparison
| Parameter | EP1S25F780C5 | EP1S25F780I6N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,249.50 | $1,250.00 |
| Family | Stratix I | Stratix |
| Logic Elements | 25,660 | 25,660 |
| Logic Array Blocks (LABs) | 2,566 | 2,566 |
| Total RAM Bits | 1,944,576 | 1,944,576 |
| Embedded Multipliers (DSP blocks) | 80 (typical) | β |
| User I/O Count | 597 | β |
| Package | 780-FBGA (29x29 mm) | 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | 1.425 V to 1.575 V | β |
| Speed Grade | C5 | 6 (I6 - industrial) |
| Operating Temperature (TJ) | 0 Β°C to +85 Β°C (commercial) | β |
| Process Technology | 0.13 Β΅m CMOS, SRAM-based | 130 nm CMOS |
| LVDS Performance | Up to 7.6 Gbps (claim per family datasheet) | β |
| PLLs | Up to 8 per device | β |
| Global Clock Networks | 14 | β |
| Mounting Type | Surface Mount (SMT, BGA) | Surface Mount (BGA) |
| RoHS Status | Compliant per Altera product page | [DATA_NEEDED: rohs status] |
| User I/O Pins | β | 597 |
| Core Voltage | β | 1.5 V |
| Operating Temperature | β | 0C to 85C (industrial) |
| MSL Level | β | 3 (per Partstack listing) |
| Lead Free | β | Yes (per Ampheo listing) |
| DSP Blocks | β | Yes (dedicated 9/18/36-bit multipliers) |
| Embedded PLL | β | Yes |
| LVDS Support | β | Yes (up to 840 Mbps per Altera datasheet family) |
| Configuration Mode | β | JTAG / Passive Serial / Fast Passive Parallel (per Stratix family) |