EP20K1000CF672C8 vs EP20K1000CF672C8ES Comparison
Detailed side-by-side comparison of EP20K1000CF672C8 by Intel and EP20K1000CF672C8ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel
EP20K1000CF672C8ES β Last Time BuySpecification Comparison
| Parameter | EP20K1000CF672C8 | EP20K1000CF672C8ES |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $245.09 | $285.00 |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Series | APEX 20KC | β |
| System Gates | 1,000,000 | β |
| Logic Elements / Cells | 38,400 | β |
| Embedded RAM | 327,680 bits | β |
| User I/Os | 488 (datasheet), 508 (per some distributor listings) | β |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Number of Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | β |
| Number of PLLs | 4 | β |
| Maximum User I/O Pins | 488 | β |
| Process Technology | 0.15 um all-layer copper CMOS | 0.18 Β΅m CMOS |
| Core Voltage (VCCINT) | 1.8 V (typical) | 2.5 V |
| I/O Voltage (VCCIO) | Multi-voltage (LVTTL/LVCMOS/LVDS/SSTL/GTL+ compatible) | β |
| Propagation Delay (typical) | 1.6 ns | β |
| Package | 672-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA |
| Operating Temperature | 0C to 85C (commercial) | Commercial (0C to +85C) |
| Configuration Mode | FPP / Passive Serial / JTAG | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS Status | unknown (legacy part, verify on lot) | Compliant |
| Family | β | APEX 20K (APEX20KE) |
| Logic Elements | β | 38,400 |
| Typical Gates | β | 25,920 |
| Maximum System Gates | β | 1,000,000 |
| Embedded Memory (ESB) | β | 216 Kbits |
| User I/O Pins | β | 508 |
| Speed Grade | β | C8 |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3 |
| PLLs | β | 4 (ClockLock/ClockBoost) |
| Programming Interface | β | JTAG (IEEE 1149.1 / IEEE 1532) |
| MSL Level | β | 3 (168 hours) |